Re: Cine CPU gate complexity

> I was wondering if you've tried to compile the model, and if so, how
> many gates / what type of FPGA does it map into?
>

        I'll map this in the next few days. I'll do it without the "PROM" module for now (I think Cinematronics calls it the System Sequencer module in that 19 component block diagram.)

        I'll have to look for a "real" FPGA compiler utility, as the only HDL compiler I use regularly is Synopsys, which maps an HDL file to a VLSI Standard Cell Library. I will be able to get a gate count, though (Our Std. Cell library does include some pretty complex gates, but if I'm not mistaken, each CLB of a Xilinx part can compute any combinational function of 5 or so variables, right?) I'm sure we have an HDL -> Xilinx or Altera FPGA compiler around here.

        Another problem might be I/Os. I think Steve O. told me that he had tried to do an FPGA based design, but there were too many I/Os for it to fit on 1 FPGA. Chances are it'll take 2 or 3 "big" ones (It's been about 2 years since I touched an FPGA, so I don't know what the "big" ones are nowadays.)

Joe
  
Received on Thu Jun 26 11:31:17 1997