RE: FPGA

>G'day folks,
>
>So as long as we are out on RAM tangents, can I ask if there's a 4:1
>ration of DRAM to SRAM how does the recent IBM (or was it Intel) memory
>breakthrough of 2 bits per "memory cell" affect this ratio? Can I
>assume that it just brings SRAM storage capacity closer to DRAM storage
>capacity?

The ratio used to be a lot easier to follow earlier on-- 1Kx4 SRAMs were
out about the same time 16Kx1 DRAMs were big, 2Kx8's were with 64Kx1's,
8Kx8's were with 256Kx1's, 32Kx8's with 1Mx1's, 128Kx8 with 4Mx1's, 512Kx8
with 16Mx1's. I think DRAM research is really outpacing "standard" SRAM
technology now though, so you'd need to be comparing Burst Mode Cache SRAM
to those big 64M DRAMs. I don't know if that still "works".

>I do understand that the breakthrough applies to flash and I'm just
>using the term SRAM interchangeable (and perhaps inappropriately).

Right, I dunno for sure what Intel uses for their Flash stuff, but it's
probably something like the "Fowler-Nordheim" tunneling that's used in
EEPROMs. Anyway, I don't think it'd really apply to the process and deisgn
of SRAM cells...

-Clay

Clayton N. Cowgill Engineering Manager
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Received on Tue Oct 7 11:39:45 1997