Re: Cine CPU exorsisor data up

Hey All,

        It looks like there is a significant interest in a mock-up
of the Exorcisor, as I expected.

        As promised, the Verilog model WILL be done today. I am
putting the finishing touches on it now. What I am going to do is:

        1) Find out if we have Synopsys FPGA compiler here. If so,
my work is done (as far as the "guts" of the Exercisor go)

        2) If we don't, I'll see what FPGA design tools I have access
to. I KNOW the apps. guys here use Xilinx and Altera FPGA stuff, so
there's gotta be some way I can use it. I think MAX-PLUS (Altera's
FPGA design tool) can read Verilog files.

        3) If all else fails, I'll go back to good 'ol PALASM.
I'll check on the prices of AMD's MACH series HD-PALs. I think the
exercisor will fit on 3 22V10s (It has 27 outputs which actually
toggle) and those run about $5 a piece, but a single MACH may be
cheaper? Like I said before, if I do this, I need to convert
my code to PALASM, but that shouldn't be too hard, since I've used
PALASM before. I think my programmer can program MACHs.

        Dave, do you have a list sitting around of the actual vectors
that come out of the exorcisor? I'd only need the first few. You DID
put the signatures on the schematic, but for debuging my Verilog
model, it would be helpful if I had a few of the actual vectors. If
you don't, I can figure them out by hand...

        I'll keep you guys posted. I don't expect the design cycle of
this whole thing to take too long.

Joe

------------------------------------------------------------------
Joseph J. Welser jwelser@ccwf.cc.utexas.edu
Design Engineer -- Crystal Semiconductor Corporation
Ph.D. Student in E.E. -- University of Texas at Austin
Work: jwelser_at_crystal.cirrus.com http://www.crystal.com
P.O. Box 17847; Austin, TX 78760
------------------------------------------------------------------
Received on Wed Oct 15 15:30:02 1997