Re: Sega Multigame and Vector Generator Card...

On Tue, 16 Dec 1997 11:56:35 -0800, Clay Cowgill <clayc@diamondmm.com> wrote:

>
>Sounds good. Zonn must be busy working. I can't believe he's resisting
> from commenting so far. ;-)

Yeah yeah yeah!!

(Just don't let anybody here at work know I've spent time on this or they'd
freak!)

I can't really describe what I mean by self clocking without a diagram. I used
ORCAD and have created a file designed for an HP Laserjet 4si. (Anybody know
how to get a graphic file -- .BMP or something -- of the schematic from an ORCAD
capture?)

Definitions:

LLC = Line Length Counter
BCR = Bresenham Control Register

So here's what it does:

The CPU would start things by loading:

- The increments used when the BCR is positive and negative.

- The starting addresses of the DAC counters if the trace is to be moved to
another starting point.

- For even lines (same small segment lengths on both sides of the line), the
initial BCR value is preloaded.

- The X and Y Master selects are setup to indicate which counter is the master
(incremented on every clock pulse) and which one is incremented only when the
BCR is negative.

- The Inc/Dec inputs are set to indicate which direction the lines is to be
drawn.

- The line will begin drawing upon loading of the Line Length Counter.

Theory of operation (except where indicated all logic is active high):

The [CLK] begins when the sign flag of the LLC is set to low (in this case the
ENB going into the [CLK] is active low).

The [CLK] output is either divided by 5 or 7 depending on which divider is
selected by the sign flag of the [BCR] which goes into the clock [mux].

Also selected by the [BCR] sign flag is the increment being fed into the [ADDER]
which is used to update the [BCR] register on each clock. (Note the add takes
place on the rising edge of the clock, while the [BCR] is updated on the falling
edge.)

Depending on how X Master Sel and Y Master Sel are setup, and the state of the
[BCR] sign flag, one or both of the DAC counters will be updated.

This is all typical Bresenham stuff except for the 5 and 7 dividers. Those are
used to auto clock the trace which will allow all traces to be drawn at the
proper speed.

This is done by knowing that one cycle of Bresenham clock can only do one of two
things:

A) Clock a single DAC counter, in which case the trace will move in a vertical
or horizontal direction.

B) Clock both DAC counters, in which case the trace will move in a diagonal
direction.

Now assuming the vertical and horizontal resolutions are equal. All movement
will be in a square. So if a horizontal or vertical movement is made the
distance moved will be "D". If a diagonal movement is done the distance will be
SQRT(D+D) or 1.4142D.

If the Divide by 7 is selected for diagonal movement and the divide by 5 used
for horizontal/vertical movement, then the time allocated for a diagonal
movement will be 1.4 times longer then that of a horz/vert movement.

Each movement of the trace will wait for the proper amount of time, and the
trace as a whole will reflect this same time. For instance a completely
horizontal line will be drawn in T time, while a completely diagonal line will
be drawn in 1.4T time. On the opposite end of things each microstep will also
be the proper amount of time so there will be no "hot spots" on the line
segments.

By setting the Neg and Pos Inc registers to 0, and setting the [BCR] to a neg or
positive number, horizontal, vertical, and diagonal lines maybe drawn.

Note: There are some bugs and omissions in the pseudo schematic, but it should
be enough to show what I'm talking about.

-Zonn

(Sure wish I had the time to place this is an PLD myself :^( )

<><><><><><><><><><><><><><><><><><><><><><><><><><><><

 ------ ___ Member of A.A.C.S.:
 |---- | ( ) Association for Artistically
    / / ( () ) Challenged Signatures
   / / //\\ // (__)
  / ---/ // \\ //\\ // zonn @ zonn . com
 -------| // \\/

Received on Tue Dec 16 15:28:23 1997