>Funny, if we used serial DACs we might as well go ahead with Al's idea to
>do serial addition. Then all we'd have is some registers shifting around
>through 2 or 4 1-bit adders and out to the DAC. WOW! Now 24 shifts at
>3-4 times the asteroids clock speed is probably too fast for anything cheap.
>Can the PLD run at ~100MHz?
Theoretically we've got up to 125MHz. In practice though you need to feed
terms back through the arrary, so any particular design won't have 125MHz
raw speed. The good news is that timing is very predictable in a CPLD (as
opposed to an FPGA which can get ugly fast). I think 40-60MHz is probably
pretty do-able. Just don't expect to get any TV reception near the card
when it's operating. ;-)
-Clay
Clayton N. Cowgill Engineering Manager
_______________________________________________________________________
/\ Diamond Multimedia Systems, Inc. clay@supra.com
\/ Communications Division http://www.supra.com/
Received on Thu Dec 18 10:24:44 1997
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