Re: Sega Multigame and Vector Generator Card...

> Devices are available in 32, 64 and 128 "Macrocells". Each macrocell is
> about like a 22V10's macrocell, but with more product terms coming in.
> Your numbers look about right-- there just aren't as many macrocells
> available as in an FPGA. (For Cypress a 24 bit ripple adder would take
> about 168 product terms, 48 Macrocells, and 24 passes through the array
> (ouch). A full-carry lookahead would eat more product terms-- ~300, and a
> few more macrocells ~56, but take MUCH less time-- 6 passes through the
> array.)

Clay (and anyone else who might be interested)
please read all this crap and see if I make sense :-) It's a bit long.

Consider this:
X = 24 bits = 3 bytes same for Y
dX = 16 bits = 2 bytes same for dY

write this as follows where x3 is most significant byte etc...
X = x3x2x1 Y = y3y2y1
dX = dx2dx1 dY = dy2dy1

Using an 8-bit adder the plotting cycle becomes:

Load X,Y to the DACs
add x1, dx1
addc x2, dx2
addc x3, sdx2 - add sign bit of dx2 to x3 along with the carry
add y1, dy1
addc y2, dy2
addc y3, sdy2 - you know.
add count, -1
repeat until count = 0

The idea here is to use an 8-bit adder & make up for it with the clock speed.
if there's room you can do curves by throwing in:

add dy1, ddy
addc dy2, sddy - use only 8bit for ddy & sign extend to 16 (like dy)
add dx1, ddx
addc dx2, sddx - same for ddx

Lastly, when I was thinking about all values being 24-bit I thought of
making a ring of registers (like 24 parallel circular shift regs) where
each value would load into the next register each cycle. 2 of these
would feed into an adder like so:

   __________________________________________________
  | |
  |__|---| |--| |--| |--| |--| |--| |--| -------
     |mux|->|r1|->|r2|->|r3|->|r4|->|r5|-+-->|r6|--> |adder|
 ----|---| |--| |--| |--| |--| |--| | |--| -------
                                         | ^
                                         |______________|

The multiplexor is simply for loading the registers from an outside
source. Once loaded, operation would simply follow the circle going all
the way around for each plotting cycle.

The registers would be loaded as follows:
r1-ddy
r2-dy
r3-Y
r4-ddx
r5-dx
r6-X

*** important ***
You'd need a set of gates between r5 and the adder to Zero it out
when r5=Y & r6=ddx also when r5=X & r6=ddy. (you don't want to
add these pairs, just pass r6 through by adding zero)

This strategy could also work 1 byte at a time if there was a carry bit
preserved (you just wire the adder to r15 and r18) which allows very simple
loading 1 byte at a time. However it seems to break down when the variables
have different number of bits(bytes) :-(

The other problem is that you need to perform one full cycle per dot
plotted and the clock speed starts to go up with all those registers
needing to go around.

Comments on this are most welcome. Unless you think I need to be
locked up :-)

--
 ___   __   _   _  _
|   \ /  \ | | | || |       phkahler@oakland.edu     Engineer/Programmer
|  _/| || || |_| || |__     " What makes someone care so much?
|_|  |_||_| \___/ |____)      for things another man can just ignore. " -S.H.