Re: Atari Cat boxes

"Ok -- I'm gonna launch off into fantasy land..

It would be nice to have an interface (pci/isa) to a 40 pin dip (and
whatever else, like an atari test connector, etc..) with each pin
being fairly controllable for i/o. I'd actually like to have another 16
or 32 random IOs to hook up to various test points...
"

I thought about this a month or so ago, and the problem you run into is
when you have a synchronous memory design, where you have to reference
memory or I/O timing to the clock on the board you're debugging. You
can't just wiggle the I/O pins in software on the PC and have the
interface work. You run into this on older Atari games where they play
the trick of cycle stealing memory accesses on the other half of the
CPU clock..

This was why I was talking about CPU-specific state machines which
could be clocked from the on-board oscillator..

You would pass it a starting adr, than 'read' or 'write' commands
and then watch a 'done' bit (or you could bring out a 'wait' line)
when the memory operation is finished. You could get fancy and have
an internal auto incrementing adr register too, since the operations
are all on 8 bit quantities.
Received on Wed Dec 31 13:08:34 1997