Re: Atari AVG Controller

> Like I need another project... not. But I need some guidance at least
> from all you PAL/PIC/GAL people. Since this IC has ram in it, is that
>the part that is throwing the wrench into putting this onto a basic PAL?
>What programable IC's would this circuit fit onto? It is such a simple
>circuit, can it be that hard? I would be interested in getting at least
>20-25 of them if I could be done somehow.

I went down this path once before. I have the entire thing designed out in
TTL, and placed and routed on a PCB. Even have parts to build 10 or 20.
The only gotcha was that the PCB is kinda large to accomodate all the 'LS
type chips.

My original poll was looking for who was interested and would you want to
pay $20-25 bucks a pop for them. (The PCB's in low quantity were around
$12-15 each, so if you add in $3-5 worth of chips and some $$$ for
time/assembly they were in the $20-25 range.)

The consensus seemed to be that $30 Space Duel boards were relatively easy
to find and except for a couple people nobody was interested so I didn't
make any.

That having been said...

Are enough people interested that I could do a run of 40-50 boards? That
should be enough to keep the price at or under $20 I'd think... (Since it
then makes sense to buy chips in quantity 100+ which helps costs and the
number of boards keeps the setup fees down.)

I looked at the CPLD/FPGA angle too. The circuit isn't really complex
(it's really just 133% of the discrete stuff you see on Tempest to do the
Vector Address Generator), but it has some wide counters and 12bit wide
registers (I think four deep) for a stack. The twist was:

Plan A: CPLD only. Maybe do-able with big enough CPLD. Cost wasn't too
bad-- around $10 for the part, but the bigger CPLD's won't fit inside the
footprint of a 40 pin dip so the PCB cost still added another $5-7. Have
to implement design in Synario or some HDL, or Viewlogic. Kinda involved.

Plan B: CPLD + register file chips. ('670s) Cheaper CPLD (for counters,
muxes, and logic) for around $6, register files added maybe $1, now you
need a bigger board to hold the extra chips and I/O's might be a problem on
the CPLD's. Same complications as Plan A for designing the thing.

Plan C: FPGA. Needs an external boot memory, dev. tools not handy, needs
big PCB because of footprint size, pain in the rear to hand solder. I
didn't want to deal with it. (singles pricing for the cheapest Xilinx part
plus a serial configuration memory is about $18 from Digikey-- and I'm not
sure the design would fit in that part either.)

Plan D: TTL on a big PCB. Easy to implement. Big PCB adds cost, chips
are relatively cheap though.

For just cranking something out that'll work I liked Plan D. For a cool
project I liked Plan A. But, I have enough cool projects so I didn't want
to take on Plan A. The FPGA route might be good if you could get a
high-enough density FGPA for the Xilinx 4000 series quantity pricing --
around $3 per chip plus about $.75 for the serial memory.

-Clay

Clayton N. Cowgill Engineering Manager
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Received on Wed Jan 7 16:31:11 1998