AVG ASIC...

I printed out my AVG ASIC replacement design file and brought it with me. :-)

So... What's different...

Open up Jess' avg_controller/schematic.gif from the address posted
yesterdat and follow along. Basically the only real change is the width of
the address bus.

Instead of everything being 12 bits wide it's 14. Looking at the clock
input to the stack pointer (K4 in the schematic on Jess' page) the ls08,
ls32, and '74 are not included in the actual ASIC. (So the input to CK is
just "/strobe1".) The DMAPUSH and DMALD (push and pop) are handled a bit
differently opcode information is brought in from the state machine with
strobe signals and are used to internally generate /GW and /GR for the
'670s. Increment for the counter array is generated internally too. The
buffers are more like ls244's since you have 14 bit wide data instead of
the 12 bits that fir nicely on two '367s.

Soooooo...

One macrocell for each bit of stack: 14 * 4 = 56
One macrocell for each bit of vram address generator: 14 * 1 = 14
One macrocell for each bit of stack pointer: 2 * 1 = 2

Buffers should be free with each macrocell. Might need one or two more for
the combinational stuff, but I think it'd probably fit in each macrocell
above...

So the total is around 72-74 macrocells. Distressingly close to the
cheaper 64 macrocell devices (missed if by *that* much... *sigh* :-) but an
easy fit into a 128 m-cell CPLD.

Hmmmmmm... I already have the Lattice CPLD stuff set up (with in-circuit
programming) and a 68pin plcc-> DIP convertor board to do my little
vector-generator project. I'll take a look at it tonight. I wonder if
there are any 128 macrocell 44pin SSOP CPLD's out there?

-Clay

Clayton N. Cowgill Engineering Manager
_______________________________________________________________________
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Received on Thu Jan 8 11:45:00 1998