"2. A complete redesign. Not just a catbox "improvement". Here I think
that an ICE would be the best. Anyone willing to help architect this?
It could go as far as being customized to ICE the favorite game
processors -- 6502, 6809, Z80, etc.
"
I'll take on #2.. It sort of dove tails with something i'm working
on at Apple right now. Part of the project i'm working on has a PCI
card with a PLX slave bus adapter. I can use a modification of this
card to build a 'bus window' card that maps two 64k regions of memory
(one for I/O, one for memory) out to a pod that generates I/O or
memory access cycles and brings back data / and status signals. Each
CPU would require a unique adapter pod to pin out the signals
appropriately. Current thoughts for support are 6502/CAT, 6809, Z80,
and 8080. The other two could be 8088 for Gottleib games, and 2650
for Meadows games.
I could use some help on the state machine designs for the pods (and
then there's the software effort..). I'm also wondering if it makes
sense to put space for the uP on the pods (which adds a lot of
complexity muliplexing the data paths) or just stick with simulation
of the CPU.
Received on Fri Jan 9 09:05:49 1998
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