Omar, you have it right.... but converting it back would be nasty.
Most of the PLD design stuff goes like this: you give it your
logic equations or state machine design or whatever in a script
language, then the software compiles it into a fuse map (the
jedec file) for a specific PLD or PAL.
The problem with going backwards is that there is a logic reduction that
goes on during the compile... if you've ever heard of Karnaugh maps,
you know what I mean. It fits the equations and stuff from your logic
design into the minimum/best gate configuration....
Technically, you can take the jedec file and the chip technical details
(if you can dig em up) and figure out exactly what is going on. BUT, the
better way is to re-engineer the chip based on what you figure it should
be doing rather than trying to replicate exactly the original design...
just my $0.02...
Mitch
On Mon, 25 May 1998, Omar Vega wrote:
> Kev,
> That's probably a JEDEC file used in programming many PLDs. They tend to be
> device specific "fuse maps" so converting one into a generic logic gate
> equivalent may be difficult. I've never bothered trying but I will double
> check to make sure this is the case when I get to work tomorrow. Thanks.
>
> Omar
>
> Kev wrote:
>
> > I know this is a bit off topic but this is best way to reach the
> > brightest minds of the collecting/gaming community.....
> >
> > I have a JED file on disk, can this be converted to a logic gate
> > equivalent?
> >
> > The reason that I ask, this chip is used on a auxilary board plugged
> > into a Pac-Man pcb to run a few different games and if I can dechiper
> > what it is doing, possibly these games may be emultated and run on a Pac
> > board as EPROMs only.
> >
> > Thanks,
> > --
> > Kev Mowerman@erols.com >>REMOVE THE ? to REPLY
> >
> > Looking for Pac-Man related hacks & Video Game
> >
> > Coin Op Page -> http://www.erols.com/mowerman
>
>
>
> --
> omar@techsource.com
> -- please use above address to reply, anti-spam in effect
>
>
>
Received on Mon May 25 20:38:16 1998
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