Re: Cat Box

Hi David!

I would rather recommend that this be built to run off of an AT bus
card. The reason is that one could then test the board under closer to
game memory speeds, and this is often a problem. Memory can work when
run slow, but fails when run at rated speed. Also the tests would be
much faster... It would not require a major design job to kludge up an
interface card...

John :-#)#
David Shoemaker (Comforce/RhoTech) wrote:
>
> I have been looking over the Cat Box schems with an eye on what I can do for
> the Switch Board.
>
> The inputs on that board are:
> A 4 row 6 col switch matrix composed of
> 16 position kbd
> (0 / 4 / 8 / C col 1)
> (1 / 5 / 9 / D col 2)
> (2 / 6 / A / E col 3)
> (3 / 7 / B / F col 4)
>
> (Col 5 below)
> "Error Data Display" Game / Tester 2 pos switch
> "Address Increment" NO momentary switch
> "Data Set" NO momentary switch
> "Tester mode" (R/W) / Signal analyzer 2 pos switch
>
> (Col 6 attached to row 3 / 4 only)
> "Read / write mode" Static / (off) / Pulse 3 pos center off switch
>
> The "Data probe" logic probe is a bit of circutry which is primarily used to
> fee the active low SRDATA signal at pin 11 of C2 on the logic board. There
> needs to be some circutry used to issolate the CB from the circut under test
> but probably not any where near what they have now as they are also
> supporting the logic probe lights and clocking.
>
> Then there are some stand alone switches:
> "Tester reset" NO momentary switch
> "Tester self test" 2 pos switch
> "Read / Write" 2 pos switch
> "Bytes (1024 / 256 / 1)" 3 position center off switch
> "DBus source (Data / Active high Address / Active low address)" 3 position
> center off switch
>
> The last section of switches are the signal analyzer triger control switches
> which XOR (using a 74LS86) the input signal with a pullup high or gnd.
> "Start" 2 pos switch
> "Stop" 2 pos switch
> "Clock" 2 pos switch
>
> Then finaly there is the display section
> 6 7-segment leds (with decimal point) 4 for address 2 for data
> 3 stand alone leds arranged so they act as the F , G and dp segments of a
> 7th LED
> Looping (F)
> Unstable Signature (G)
> Compare Error (dp)
>
> Then there is a stand alone led just hanging off an input from the logic
> board called "Gate" (pin 1 of the interconect)
> These are all driven by signal from the logic board thru a driver
> transistor, the selection between the leds is done by a 74LS42 BCD to Dec
> decoder
>
> Then the final part of the whole thing is:
> "No clock" led which is being fed by half 74123 retrigerable monostable
> multivibrator.
>
> Now what does this get us. If we were to try to build a computer interface
> I am thinking a bi-directional parallel port interface as this gets more
> lines thru at one time and that goes along well with the parallel data
> nature of the leds.
>
> So we would have to have a set of latches to pretend they were the switch
> matrix. Not too tough.
> And we would have to have a set of latches to pretend they were the
> display's. Once again not to bad.
>
> The XOR's for the probes are still needed but could perhaps be moved into
> the "chip". Joe?
>
> I am still in the brainstorming stage of this so let me know if any of you
> brain trust types has any thoughts.
>
> David

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