RE: MM2114N RAM Replacement

> There were a couple of reasons why I warned against using
> 450 nS RAM with a 1.5 MHz 6502. [...]
         Addressing isn't guaranteed to be valid until the
> start of phase 2 and data isn't guaranteed to be held past the
> end of phase 2. Put those two things together and you are
> probably violating timing on a 450 nS part, even with only a
> 1 MHz clock!
>
*My* memory must be having timing violations. ;-) I thought the Phase 2
signal was just half-clock 180 degrees out of phase with the Phase 1
signal... (and used to qualify outside memory access?) Maybe I've got
myself confused.

Atari *did* like to tie Phase 2 in as a qualifier for stuff, although I
don't think you have to. Lots of stuff I've run across seems to just
use R/W directly to the SRAM to control read and write, with CS being
generated from an LS138 or LS139 on the upper address lines. Your SRAM
is only reacting to the changes in R/W which is the external R/W signal
and the CS from the memory decode-- both of which seem to never happen
at full bus-rate.

Could be that those designs were just lucky and had SRAMs that were
running at better than rated speed though. (I remember thinking there
was "no way" 450ns EPROMs could work-- particularly with LS245's on the
data bus and three-levels deep of LS-series memory decoding, but when I
actually worked through it it looked perfectly safe (to my surprise).
That was a long time ago though so maybe I was just freaking out at the
time or something. ;-)

-Clay
Received on Tue Mar 30 19:50:00 1999