Re: Z80

On Tue, 27 Jul 1999 14:39:00 -0600, you wrote:

>Is anybody on here an expert on the Z80?
>Specifically, how does the Z80 refresh dynamic memory?

        From THE Z-80 MICROCOMPUTER HANDBOOK, page 28:

        "Typical dynamic memories are set up so that a refresh cycle can be
input into the memory, along with five or six address line inputs. To
refresh an entire memory, six address line inputs would require sixty-four
separate refreshes (2^6) with the entire refresh cycle lasting no longer
than 2 milliseconds. When the output signal RFSH* is low and signal MREQ*
is also low, external dynamic memory will use the contents of the
least-significant bits of the address bus to implement one of the refresh
cycles. RFSH* is active at every instruction fetch, and since the R
register is continually being incremented after each fetch, the address
lines will continually reflect a new address for the next refresh cycle."

        As Christopher pointed out, the I register winds up on the upper 8 bits
(A8-A15) of the address bus during this cycle... but this is just a
consequence of the I and R registers being internally "paired" in the
Z-80's internal data paths. It is not really useful to you in implementing
DRAM refreshes, because the I register is used to hold the upper 8 bits of
an interrupt-vector table when using the Mode 2 Interrupt method (which I
won't go into here), so it _never_ changes unless your program explicitly
modifies it.

        As to how that translates to actually _interfacing_ DRAMs to a Z-80...
that gets a little trickier. :) The Z-80 was designed back in the
mid-to-late 70's, don't forget, and so its internal DRAM-refresh capability
was designed with that era's parts in mind. DRAM is generally organized by
rows and columns, and the design assumption made by the Z-80 is that your
DRAM's use column-mode refreshing - i.e. that a refresh cycle initiated on
column X will cause every row cell in that column to be refreshed. (Which
describes practically every 70's/80's-era DRAM that I know of, but I
include the caveat because I'm sure _someone_ out there can provide an
example of it being done some other way. :) ) Since the R register is only
7 bits wide, so your intended DRAM can't have more than 128 columns.

        If you need more detail, I'll have a look for my Zilog databook and see
if I can't scan and e-mail you the relevant pages...
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Received on Tue Jul 27 21:33:10 1999