Re: Wong data for the Y DAC (Tempest)

Rodger Boots wrote:
 
> The high bit determines which half of the screen,

Interesting info!
Is the data fed to the DAC coded like in two's complement coding?
Hmm, I will test immediately wether this bit goes high sometimes at this
test screen or not.

I can remember I saw a negative Y at the output of the opamp in normal
play mode, and I have also checked all bits to be active; they are. This
was the first thing I checked; to see wether all bits are 'alive'.

> so take a look there to
> see if it goes to both states or not. Also look at the output of the DAC
> where it feeds the opamp. You should see zero volts there with maybe a
> little noise, but you should NOT see anything swinging one side of zero.
> That would indicate an opamp problem.

Thanks due to this same advise you gave me before I replaced the Y I/U
opamp before, and ever since then I see a normal virtual ground there
and normal I/U conversion. I am sure the problem is really the data send
to the DAC, not the DAC or adjecent analog circuitry. (I tested the DAC
in another, working boardset and it turned out to be ok (I sockeded
everything so this is done easily) :)

> Also check + and - power supplies
> going to the DAC and opamp. Any of these missing will cause your problem.

These are all nice and clean.
I am really afraid it is a little more difficult, involving the Vector
Shifter and such circuitry. Problem is, I cannot find a description of
the digital Vector part's theory of operation...

Thanks for your input, I really appreciate it.

>> Tek Wrote:

> > Did anybody ever see that the XDAC was fed with the right data, but the
> > Y DAC with completely wrong data? (for example, in the large '+' test
> > screen, the X output shows correct,(a positive-negative going triangle
> > wave), the Y shows only one big positive going sawtooth).
> >
> > I am sure the DAC's itself are OK, as well as the analog circuitry
> > around them.
> >
> > My first guess is, that the cause could be the Vector Generator Data
> > Shifer circuitry. I believe this piece of hardware 'grabs' the X and Y
> > data from the databus, and thus could cause erratic Y data, and correct
> > X data.
> > Am I right here?
> >
> > If ths is not causing the trouble, the data on the bus itself should be
> > wrong, but only for the 'Y' output. has anybody ever seen this before?
> >
> > Is there theory of operation somewhere on the net, which describes these
> > digital circuits?
> >
> > Thanks a lot guys!
> >
> > Mendel
Received on Sat Nov 27 15:01:13 1999