Re: DVG Multigame

On Thu, 9 Mar 2000 19:34:11 -0800 (PST), Neil Bradley wrote:

>Hardware-wise, we need a PAL (or something equivalent) to do the
>following:
>
>* Invert A15 to the new EPROMs output enable
>* Have any write to the 8000-ffff region go to an 8 bit latch. The bottom
> two bits to go the upper address lines on the vector EPROM (27256) to
> select which bank of 8K the vector generator should use.
>* Exclusive OR the PROM/VRAM output select (one half of L2) on the vector
> generator, and have it drive !OE on the vector EPROM (27256).

        This seems like such a simple set of requirements, it seems a shame to
go to all the trouble of making a PAL - a couple of 74-series TTLs should
do just as well, I would think. An 'LS86 quad-XOR gate should handle the
OE* and inverted A15 problem, and an 'LS377 octal-D flip-flop to handle the
latching. (Actually, any old D-type flip-flop package should work, since
you don't seem to _need_ all eight bits, or any tristate outputs.)

        _Maybe_ a third quad-gate chip of some kind (NAND, NOR, etc.),
depending on how a "write to the 8000-FFFFh region" is to be decoded.
(Personally, if there's already some kind of Memory-Write-Enable signal
available, I would just look for A15 to go high while MEMW* goes low, and
have that condition generate a positive-going edge to the 'LS377 latch,
thusly: <<warning - bad ASCII art ahead! :) >>

                   ______
A15 --------*----\\ 1/4 \
            | ||74LS86|---*--------------------------------- CPU_A15*
             ----//______/ |
                              | _________
                               --------------------|G* 7 |
                   ______ | 4 |
MEMW* ------*----\\ 1/4 \ | L |
            | ||74LS86|------------------------|CLK S |
             ----//______/ | 3 | VectorROM
                                                   | 7 | BankSEL
D1-------------------------------------------------|2D 7 2Q|---- A14
D0-------------------------------------------------|1D 1Q|---- A13
                                                   |_________|

        This, of course, assumes that both the CPU address and data buses
become valid a sufficient amount of time before MEMW* goes low, so the '377
latch can respond to the change in G* stage; if there's a timing issue
there, it would be better to hold G* low and then NOR the MEMW* and
CPU_A15* signals into the '377s CLK input.

        I know, it's not as sexy as a PAL, but I'm a great believer in keeping
things simple and straightforward. :)

        (DISCLAIMER: I wasn't actually looking at the Asteroids schematic when
I cooked this up, so this is purely "educated guess" material based on
Neil's description of the problem.)
-----------------------------------------------------------------------------
BREAK UP MICROSOFT!!
(Preferably with a wrecking ball and some dynamite.)
---------------------------------------------------------------------
solarfox@DON'TMESSWITHtexas.net (Gary Akins jr.)
http://lonestar.texas.net/~solarfox
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Received on Fri Mar 10 00:39:32 2000