Re: DVG Multigame

> allowing it to count on the next low-to-high transition of CLK. Then,
> presumably, when MEMW* goes low, it too gets inverted and fed to the latch,
> where it clocks the data on D0-D1 through to the ROM addressing lines.

Yes, it looks like that'd solve the bank switching vector ROM issue.

> There would almost certainly have to be a Memory-Write-Enable
> _somewhere_ on that board, and A15 can be picked directly off the CPU if
> necessary (I thought you said there was a pad on the PCB for it, though?).

Currently the way A15 is wired to the address decoding circuitry, A15
isn't used, so everything is mirrored. There are pads to wire it to A15 on
the processor

> >> I know, it's not as sexy as a PAL, but I'm a great believer in keeping
> >> things simple and straightforward. :)
> >Oh, me too. I just don't know any better. ;-)
> ::tsk:: What _are_ they teaching in the schools these days... :)

Heh. Well, that would require that I had gone to school for electronics.
;-) I'm a software guy mostly, and all my electronics training is in
analog circuitry.

> something to prevent the design from being stolen. I just dislike the
> "black box" aspect of them; they make the board that much harder to
> maintain and troubleshoot later.

Sometimes it saves components. I have someone on the sidelines offering to
make a one-size-fits-all chip for me which makes my hacks less extensive.

> >But how would we handle the 2 to 4 address decoder/enable on the vector
> >generator? Two bits going in to select which part of the 1K area the
> >vector generator owns and 4 not bits coming out. We need to do a !OE
> >on 3 of the 4... wait a sec... an inverter would work here.

On second though, that won't work because there's another qualifier
line...

> Hm - looks like I'd better go download a copy of the schematics, so I
> have a clearer idea of what you're up to...

Hopefully this will shed some light.

There's half an LS139 that takes two address lines as inputs. There are 4
outputs - 3 of them go to VROMs, one goes to VRAM. In the "real world" of
the board, 4000-47ffh is vector RAM, and 4800-5fffh is vector ROM. At the
basic level, I need to be able to map ROM over the top of the 4800-5fffh
region but not enable the chip's output when it's at 4000-47ffh. Normally
three of the outputs of the LS139 go to !OEs - vector ROMs. Somehow I have
to take those three lines and turn them into one big !OE if any of them
are low.

-->Neil

-------------------------------------------------------------------------------
Neil Bradley Seti@Home Hall of Shame on a 80386DX16, Intel 80387
Synthcom Systems, Inc. 32MB RAM, Win 95 Status: 48.425% complete
ICQ # 29402898 CPU Time: 1721 Hours 14 minutes 53.4 sec

---------------------------------------------------------------------------
** To UNSUBSCRIBE from vectorlist, send a message with "UNSUBSCRIBE" in the
** message body to vectorlist-request@synthcom.com. Please direct other
** questions, comments, or problems to neil@synthcom.com.
Received on Fri Mar 10 13:40:12 2000