Re: AVG register file depth (!?!)

Hi James,
 
    I am pretty sure it was only 3 levels deep. I had played around with this using an Altera PLD once via schematic entry. I know that mikej @ fpgaarcade.com has implemented most of Star Wars in an FPGA, so you might want to shoot him an email....he's probably done this already and can probably test your code for you (assuming that Star Wars uses the AVG....I forget to be honest).
 
    While the schematics show a 4x12 register file, I suspect the actual masks only implemented 36 flops as opposed to 48. Any access to the "4th level" results in a garbage read/write if I am not mistaken. I do know that on old Atari ASIC schematics (like TIA for instance), there are numerous notes on the schematics where a circuit is repeated, yet a note indicates that something is slightly different in one instance (TIA 1st bit of the playfield playfield logic for example). I know this is not spelt out on Jed's schematics, but I am pretty sure I have read on numerous occasions that the stack is only 3, 12 bit words deep....maybe Jed was simply copying the schematics he had to some new tool and simply omitted any implementation notes.
 
    What you could probably do is simply use generics in the VHDL and have the user select the # of rows to use....just a suggestion. That way, all the user will have to do is use an instantiation template or simply modify the code theirselves. That allows the user to use any PLD they wish. Just note that this is an unknown for now in the source code.
 
Ed

 
----- Original Message ----
From: jrok <jrokweb@san.rr.com>
To: vectorlist@vectorlist.org
Sent: Sunday, August 27, 2006 6:13:13 PM
Subject: VECTOR: AVG register file depth (!?!)

Hey all,

Ok, so who can answer this.. Jed Margolin's notes on the AVG specify that
the stack/register file is only 3 levels deep, his schematics and the
replacement boards use a 4 level deep register file. From testing, but
only with spaceduel as I still have to fix my blackwidow boardset ;), a
3 level deep stack appears to works fine...

So anyone know if anything makes use of more than 3 levels of stack ???

Why I'm interested ? I've developed a VHDL model for the AVG that'll fit
nicely into a 5v Xilinx XC95108 CPLD which will be published as freeware
very very shortly. A 3 of 4 level deep stack fits just fine into the 108
cell device so it's really just academic interest at this point.

- James

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Received on Sun Aug 27 21:29:27 2006