Re: AVG register file depth (!?!)

jrok wrote:
> Ok, so who can answer this.. Jed Margolin's notes on the AVG specify that
> the stack/register file is only 3 levels deep, his schematics and the
> replacement boards use a 4 level deep register file. From testing, but
> only with spaceduel as I still have to fix my blackwidow boardset ;), a
> 3 level deep stack appears to works fine...

I'd hazard a guess that the logic required for an additional stack level
pushed the chip over some design limit (probably cost-per-unit) and the
circuitry was removed.
In other words, you have a three-level stack, but seeing as the only register
files you can get easily are four-level, the replacement circuits use a
four-level device.

I think the DVG had a four level stack, but I could be wrong...

> Why I'm interested ? I've developed a VHDL model for the AVG that'll fit
> nicely into a 5v Xilinx XC95108 CPLD which will be published as freeware
> very very shortly. A 3 of 4 level deep stack fits just fine into the 108
> cell device so it's really just academic interest at this point.

Oh, cool!
I implemented the DVG circuit (all the stuff from the state machine to the
rate multipliers and DAC buffers) in Verilog. I'm just trying to get some
bigger gate arrays (maybe a Xilinx Spartan series chip) and then I'm going to
build a prototype. I've already got the DACs (Analog Devices AD5433YRU), but
the analogue circuitry needs looking at.

I've got a bag full of Xilinx chips:
   2x XC95288XL [PQFP208]
   5x XC95216 [PQFP160]
   8x XC95144XL [TQFP144]
   2x XC9536XL [PLCC44]
   8x XC9572XL [PLCC44]

I'd love to get some of the Spartan chips and some more XC95*XL chips, but
Farnell only stock the 9536XL and 9572XL. I could order some through DigiKey,
I suppose, but they ship via UPS and their 'brokerage fees' are utterly insane.

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