Re: Cinematronics CCPU on Xilinx FPGA

Sorry....this was intended to be a private email and not for vectorlist...can this be removed :-) ?!?!
This is what I get for staying up until 2:40AM.

Ed

________________________________
From: Ed Henciak <ehenciak@yahoo.com>
To: vectorlist@vectorlist.org
Sent: Tuesday, April 7, 2009 2:35:01 AM
Subject: Re: VECTOR: Cinematronics CCPU on Xilinx FPGA

 
Quit being a baby. You've got all the
free notepads and pencils that fit in the bag at the last Xilinx seminar--
how much more "simulator" do you need? When I was doing PLD's we didn't
*have* simulators. We had to carve logic gates out of scrap wood and roll
marbles through them. Ever try to XOR a marble? Damned kids these
days just spoiled with all their
technology... ;-)
 
I XORed a brick! You and your fancy marble...and to think I respected you.

I haven't been to a Xilinx seminar in my life...I get the slides knowing damn well sitting through one of those presentations would be an absolute waste of my time :-)! In fact, 3 of the 4 Webcases I filed last week are now answer records coming out with the note that "fixes will be implelemted in ISE11.1SP1. :-).

As far as simulators are concerned...I've been digging this one for Verilog :
http://www.sugawara-systems.com/index.htm

$50!!!! I ran my older PCI-Express bridge through this and it friggin ran as fast as Modelsim :-)!

I'm also 35 years old...I'm not that young :-)! I'm officially old enough to bitch about a few things that
were better back in my day ;-)!

And you'd better be sending these emails by copying text
into an open SMTP socket or something. I don't remember authorizing any
email programs!

I'm screwed there :-( ... Closest I ever came to that was using Pine back in the day when I used nothing but Unix/Linux.

 
On a more serious note...I am making slow progress with Actel...I went and got some pin migration going on, but had to go out for a couple of hours. Plus work sucked today as I found that my PHY was dead on my board (I thought I had ethernet issues in the FPGA...twas not the case). Now whats really scaring me is that the phy really shouldn't have died....after 9 years of playing with networking stuff, I never encountered a dead PHY....hopefully it was a static zap or something.

Anyway, looking at the timing and the like with Actel, this chip looks fantastic as it gives us some room to play with for future LCD antics as well as Namco (assumingt he price stays low :-) ). I just want to insure everything is OK after pins are constrained :-)! This Libero IDE has improved substantially since the last time I used it...wow! If only Xilinx could follow their lead with that rotten EDK bullshit....Actel's ARM development environment looks simple and sweet....too bad it isn't cost effective.

Ed

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Received on Tue Apr 7 02:42:01 2009