Re: Tempest Schematic error?

J7 is where OP0-2 come from (on schematic right below F5).

On Sun, Jun 27, 2010 at 12:10 AM, Kevin Moore <talon.k@gmail.com> wrote:

> Yeah I'm to the prom, trying to figure out why OP0-2 aren't making it to
> it.
>
> P7 shows OP0-1 and they are toggling. Trying to find the origin of OP2,
> then try to figure out why they aren't making it to the Prom.
>
> I've already tried swapping the prom with known good.
>
>
>
>
>
> On Sat, Jun 26, 2010 at 11:55 PM, Rodger Boots <rlboots2@gmail.com> wrote:
>
>> NO NO NO, don't tie the others high---find out why LATCH1 (inverted) is
>> staying low.
>>
>>
>> On Sat, Jun 26, 2010 at 11:51 PM, Kevin Moore <talon.k@gmail.com> wrote:
>>
>>> I haven't tried tying the others high. But no they don't pulse.
>>>
>>> I've been trying to track down the VGCK, but so far I haven't been able
>>> to find the origin. Guess my eyes are getting tired from looking at these
>>> schematics.
>>>
>>> It's looking like the VSM is dead, and it may be due to the VGCK.
>>>
>>>
>>>
>>> On Sat, Jun 26, 2010 at 11:21 PM, Rodger Boots <rlboots2@gmail.com>wrote:
>>>
>>>> I was only getting DVY8-11.
>>>> So you're saying ONLY F5 is working? I could believe that...
>>>>
>>>> Having pin 1 tied high might not be that important. A better question
>>>> is why pin 1 on the other chips is low---do they pulse at all???
>>>>
>>>>
>>>>
>>>> On Sat, Jun 26, 2010 at 9:32 PM, Kevin Moore <talon.k@gmail.com> wrote:
>>>>
>>>>> Versions 1, 2, 3 all show the same thing. Looks like a cut and paste.
>>>>> Pin 1 definitely get's hooked to pin 2 solder pad joining them. I would have
>>>>> never noticed, but I have a video problem, and I was only getting DVY8-11.
>>>>> When I started probing I noticed that pin 1 was high on F5, but not on any
>>>>> of the other Ls194 chips. So that got me off on a wild goose chase trying to
>>>>> figure out why pin 1 of the rest of the circuit wasn't connected to F5 pin
>>>>> 1.
>>>>>
>>>>> In any case, none of my latches are toggling, nor any of the states
>>>>> going into f7.
>>>>>
>>>>> So now I'm doing the logic probe shuffle in circles.
>>>>>
>>>>>
>>>>> On Sat, Jun 26, 2010 at 9:18 PM, Kevin Moore <talon.k@gmail.com>wrote:
>>>>>
>>>>>> Yeah it's an ls194 alright. But the board/s I am looking at all have
>>>>>> pins 1 and 2 shorted.
>>>>>>
>>>>>>
>>>>>>
>>>>>> On Sat, Jun 26, 2010 at 8:52 PM, Rodger Boots <rlboots2@gmail.com>wrote:
>>>>>>
>>>>>>> Printing 1 schematics show same thing, no pin 1-2 connection and chip
>>>>>>> is an LS194.
>>>>>>>
>>>>>>>
>>>>>>> On Sat, Jun 26, 2010 at 8:48 PM, Rodger Boots <rlboots2@gmail.com>wrote:
>>>>>>>
>>>>>>>> The schematics I pulled up say F5 is an LS194 with pin one being
>>>>>>>> LATCH1 (inverted) and pin 2 going to P R15. But there is a connection dot
>>>>>>>> at pin 1 and I am using printing 2 of the schematic, so on printing 1 they
>>>>>>>> MIGHT have been incorrectly connected together.
>>>>>>>>
>>>>>>>>
>>>>>>>> On Sat, Jun 26, 2010 at 6:33 PM, Kevin Moore <talon.k@gmail.com>wrote:
>>>>>>>>
>>>>>>>>> So I was looking through the schematics today, and it seems that
>>>>>>>>> there is a problem in the vector-generator data shifter
>>>>>>>>> section. Specifically with F5. Perhaps I'm just confused, so I thought I
>>>>>>>>> would ask and see. But it looks to me like pins 1&2 are tied together.
>>>>>>>>> Instead of having /Latch1 going into pin 1.
>>>>>>>>>
>>>>>>>>> Also could someone explain to me what the P,R15, and P,R31 lines
>>>>>>>>> are?
>>>>>>>>>
>>>>>>>>> Thanks,
>>>>>>>>>
>>>>>>>>> Kevin
>>>>>>>>>
>>>>>>>>>
>>>>>>>>
>>>>>>>
>>>>>>
>>>>>
>>>>
>>>
>>
>

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Received on Sun Jun 27 01:45:46 2010