> I can understand why Clay didn't make the /SAVE and /RECALL
> dependent on the /CS but it might certainly be a little safer
> to prevent glitches.
> that might be a potential reason that some 2212's were a
> little finicky in there??? Not sure, just a guess.
Honestly, I don't remember. ;-) Might have just been a matter of saving a
chip or two. Odds are good that I tried it the simplest way and didn't have
problems so I just stuck with it. (In theory the RAM array is retrieved on
power-up, write *is* gated by /CS-- so the contents would never change-- and
a save of the same data shouldn't cause problems.)
-Clay
P.S. Thinking about it some more, I *vaguely* recall something about having
to add logic to the +5EAROM power domain to gate those signals cleanly which
made me nervous... Like the main PCB logic supply would go away faster than
+5EAROM and the additional TTL gates were causing an extra
transition/glitch/timing something or other as the main VCC logic rail fell
relative to the +5EAROM. It's pretty fuzzy after all these years. I
probably saw something I didn't like, simplified it and saw it worked OK on
my boards and just used that instead. ;-)
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Received on Wed Feb 23 22:16:37 2011
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