Re: Atari AVG 137179-001 chip operation info needed

Maybe stupid questions, but are you SURE the stack is internal and not an
external RAM? Your data almost looks like an external read of pullup
resistors instead of stack RAM. Also is the very first thing you do is to
reset the chip (both through a reset pins and the reset instruction?
On Nov 2, 2011 1:40 PM, "William Boucher" <wboucher6@cogeco.ca> wrote:

> **
> Just wondering if there is someone out there willing to help me who is an
> expert in how the Atari AVG 137179-001 chip works.
>
> The chip is the analog vector generator IC used in Space Duel, Gravitar,
> Black Widow, Star Wars, Quantum. The chip has been described as a state
> machine, a custom microprocessor, and in terms of logic circuits.
>
> I am trying to put together an AVG chip tester system that can fully
> exercise the IC and tell you if it is good or not. It would be great if
> there is a detailed datasheet available for the AVG IC that someone could
> send to me (or link to) but I suspect there is no such documentation
> available. However, if someone could lend their expertise, I would
> certainly appreciate it.
>
> According to info found online, probably based on Jed Margolin's
> equivalent logic schematic (in the doc "The Secret Life of Vector
> Generators"), the IC has five basic functions or instructions...
>
> 1) Reset PC (program counter = 0, stack pointer = 0)
> 2) PC INC (increment the 14 bit program counter)
> 3) JMP (PC gets loaded with address value supplied at chip DVY inputs)
> 4) JSR (present PC value gets stored to stack memory, increment stack
> pointer, PC gets loaded with address value supplied at chip DVY inputs)
> 5) RTS (decrement stack pointer, PC gets loaded with value read from stack
> memory)
>
> So far, I have functions 1, 2, and 3 working just fine. I can't get the
> JSR and RTS functions to work. I used an 18-channel logic analyzer to
> capture waveforms from a working AVG chip while running in Space Duel. I
> compared them to the waveforms that my tester circuit is generating. I
> can't see any difference (at least none that appears relevant) in the
> waveforms produced by my tester circuit with respect to the actual game
> board, but whenever my tester circuit performs the RTS function, the
> PC becomes 0011 1111 1111 1110. I'm assuming that JSR is failing to
> save the PC value. On the plots captured from the game, I can find lots of
> examples of JSR instructions followed by PC INC's, PC JMP's, ignored
> strobes, and finally complimentary RTS instructions that do restore the
> correct PC values. The same AVG chip in my tester will not restore the
> correct PC value during the RTS instruction.
>
> My tester circuit is based on a PIC18F452 microcontroller programmed in
> CCS PIC-C. It can write to latch chips (74HC574) and some direct outputs
> to generate the OP0, OP1, OP2, ST2, ST3, STR0, STR1, STR2, and DVG0:12
> signals that go to the target AVG IC. It can also read back the AVG0:13
> value via buffer chips (74HC541). The target socket is a DIP-40 ZIF into
> which the AVG IC is inserted.
>
> There appear to be some relationships between the ST3 signal (apparently
> an AVG IC system clock) and one or more of the strobe inputs that is not
> specified by Jed Margolin's replacement logic circuitry. For example, the
> PC JMP instruction does not update AVG0 until the chip sees a rising edge
> on ST3 while the STROBE2 line is low. The other lines AVG1:13 appear to
> load immediately regardless of ST3. I am wondering if there is something
> like that, that I am missing, that has something to do with why the JSR
> and/or RTS instructions are failing. In the replacement logic circuitry,
> the ST3 signal has nothing at all to do with loading the PC so I was
> surprised to see that there is such a link within the actual AVG IC. Also,
> in the game plots, I can see plenty of strobe pulses that are apparently
> ignored due to being blocked/disabled by inactive OP0, OP2 signals. I am
> assuming that they are in fact doing nothing but how could I know for
> sure? At this point, I have no way to know if there's some unknown purpose
> for the apparently unused strobe pulses. I also noticed that the ST2 line
> is always high (to disable incrementing of PC) and ST3 is always low during
> any strobe pulse so my tester is adhering to that relationship as well.
> Could there be a special sequence that has to be executed before a JSR
> instruction to unprotect the stack memory so that a write to the stack will
> succeed?
>
> At this time, it seems like the only way to test an AVG IC is to plug it
> into a game and play the game and watch the picture for problems.
> I'd prefer to have my little tester box on the bench that can quickly and
> easily verify the operation of an AVG IC. Obviously, the tester circuit
> should work for any AVG logic replacement module as well. If I can get
> this tester to work properly, I can provide the schematic and source code
> to anyone who wants to build one. It's a bit complicated so it requires a
> solid effort. I built mine in 3 to 4 days. I've spent about as long
> writing the C program code. I've gone as far as I can go until the JSR/RTS
> issue is resolved.
>
> Any help greatly appreciated.
>
> Bill Boucher
> http://www.biltronix.com
>

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Received on Wed Nov 2 14:56:39 2011