Re: Atari AVG 137179-001 chip operation info needed

Thanks Roger, this is much closer to the type of response I was hoping for. The information about the 0,1,2 count (3 level stack, not 4) may be useful and the statement about it starting at an odd level like three and so it requiring an increment of the stack pointer to wrap it around before using it makes sense. My tester however, was already programmed to load and restore three levels sequentially so I would have expected it to save and restore at least two values out of the three, assuming that it trashed that first one. Regardless, I will factor that information in my thinking and change my program accordingly.

I understand very well how the Jed Margolin circuit works. I think that my tester would work perfectly with that logic. After all, that is the schematic that my tester was designed to work with in the first place.

A little information about myself, I have been working with, designing with 7400/4000 series logic devices since the '70's. I have been using mainly Microchip PIC microcontrollers since 1992 and have done some work with Intel 8749H, Stamp1&2, Scenix SX18/28, Atmel, and others. I got into logic replacement using Atmel and Xilinx around 2000 but I began to focus on it a lot more when I got into the arcade hobby around 2004. On my site there are photos of my Omega Race digital spinner based on Xilinx CPLD, BPROM replacements based on Atmel and Xilinx SPLD/CPLD, and the CinExor which is a new route of the original Cine Exorciser. A couple of months after I routed that PCB, I programmed a Xilinx XC9536 to do exactly the same thing as the 74LSxx based circuit. I probably should have routed the CPLD version instead because they are certainly cheaper to assemble and would have a smaller PCB.

Here's a picture of my own version of a Xilinx CPLD replacement for the AVG. I know, others have already done it ahead of me so I'm late to the party. I just wanted to take my own crack at it. I could use the VHDL programming experience and it seemed like a good place to start. I wrote the code for this in 2008 but I'm only now getting around to trying it out however first I wanted to get my AVG chip tester system working on the original Atari chips. When my Xilinx module is proven out, I will sell them if anyone wants one/any.

Here's my AVG chip tester rig. I know it's kind of a cobbled together rat's nest looking thing but it's quite solid. The base PCB is one that I designed for a totally different project way back in 1995 but out of the 100 or so boards in my collection, it was actually the best choice due to its combination of PICmicro, voltage regulator, switches, LEDs, serial port, and lots of I/O ports. It's an old base so it doesn't support in-circuit serial programming, but it is running a fast bootloader and sending text messages to HyperTerminal. It will reflash very quickly and display debug messages on the PC. The AVG chip is in the green ZIF socket and the big DIP-clamp with all the wires flying out of it is connected to a Tech-Tools DigiView USB logic analyzer.

Top view:

Bottom view:

William Boucher
http://www.biltronix.com
  ----- Original Message -----
  From: Rodger Boots
  To: vectorlist@vectorlist.org
  Sent: Wednesday, November 02, 2011 11:05 PM
  Subject: Re: VECTOR: Atari AVG 137179-001 chip operation info needed

  Did you see the "The Stack Pointer is designed to count in the 0, 1, 2, 0, 1, 2...etc. sequence, however, since power on can cause the Stack Pointer value to be 3, it is recommended that a "dummy" JSR Instruction be generated before using a real JSR Instruction." part of http://www.jmargolin.com/vgens/fig24.pdf ? Maybe that is the state you're hitting by accident.

  On Wed, Nov 2, 2011 at 1:40 PM, William Boucher <wboucher6@cogeco.ca> wrote:

    Just wondering if there is someone out there willing to help me who is an expert in how the Atari AVG 137179-001 chip works.

    The chip is the analog vector generator IC used in Space Duel, Gravitar, Black Widow, Star Wars, Quantum. The chip has been described as a state machine, a custom microprocessor, and in terms of logic circuits.

    I am trying to put together an AVG chip tester system that can fully exercise the IC and tell you if it is good or not. It would be great if there is a detailed datasheet available for the AVG IC that someone could send to me (or link to) but I suspect there is no such documentation available. However, if someone could lend their expertise, I would certainly appreciate it.

    According to info found online, probably based on Jed Margolin's equivalent logic schematic (in the doc "The Secret Life of Vector Generators"), the IC has five basic functions or instructions...

    1) Reset PC (program counter = 0, stack pointer = 0)
    2) PC INC (increment the 14 bit program counter)
    3) JMP (PC gets loaded with address value supplied at chip DVY inputs)
    4) JSR (present PC value gets stored to stack memory, increment stack pointer, PC gets loaded with address value supplied at chip DVY inputs)
    5) RTS (decrement stack pointer, PC gets loaded with value read from stack memory)

    So far, I have functions 1, 2, and 3 working just fine. I can't get the JSR and RTS functions to work. I used an 18-channel logic analyzer to capture waveforms from a working AVG chip while running in Space Duel. I compared them to the waveforms that my tester circuit is generating. I can't see any difference (at least none that appears relevant) in the waveforms produced by my tester circuit with respect to the actual game board, but whenever my tester circuit performs the RTS function, the PC becomes 0011 1111 1111 1110. I'm assuming that JSR is failing to save the PC value. On the plots captured from the game, I can find lots of examples of JSR instructions followed by PC INC's, PC JMP's, ignored strobes, and finally complimentary RTS instructions that do restore the correct PC values. The same AVG chip in my tester will not restore the correct PC value during the RTS instruction.

    My tester circuit is based on a PIC18F452 microcontroller programmed in CCS PIC-C. It can write to latch chips (74HC574) and some direct outputs to generate the OP0, OP1, OP2, ST2, ST3, STR0, STR1, STR2, and DVG0:12 signals that go to the target AVG IC. It can also read back the AVG0:13 value via buffer chips (74HC541). The target socket is a DIP-40 ZIF into which the AVG IC is inserted.

    There appear to be some relationships between the ST3 signal (apparently an AVG IC system clock) and one or more of the strobe inputs that is not specified by Jed Margolin's replacement logic circuitry. For example, the PC JMP instruction does not update AVG0 until the chip sees a rising edge on ST3 while the STROBE2 line is low. The other lines AVG1:13 appear to load immediately regardless of ST3. I am wondering if there is something like that, that I am missing, that has something to do with why the JSR and/or RTS instructions are failing. In the replacement logic circuitry, the ST3 signal has nothing at all to do with loading the PC so I was surprised to see that there is such a link within the actual AVG IC. Also, in the game plots, I can see plenty of strobe pulses that are apparently ignored due to being blocked/disabled by inactive OP0, OP2 signals. I am assuming that they are in fact doing nothing but how could I know for sure? At this point, I have no way to know if there's some unknown purpose for the apparently unused strobe pulses. I also noticed that the ST2 line is always high (to disable incrementing of PC) and ST3 is always low during any strobe pulse so my tester is adhering to that relationship as well. Could there be a special sequence that has to be executed before a JSR instruction to unprotect the stack memory so that a write to the stack will succeed?

    At this time, it seems like the only way to test an AVG IC is to plug it into a game and play the game and watch the picture for problems. I'd prefer to have my little tester box on the bench that can quickly and easily verify the operation of an AVG IC. Obviously, the tester circuit should work for any AVG logic replacement module as well. If I can get this tester to work properly, I can provide the schematic and source code to anyone who wants to build one. It's a bit complicated so it requires a solid effort. I built mine in 3 to 4 days. I've spent about as long writing the C program code. I've gone as far as I can go until the JSR/RTS issue is resolved.

    Any help greatly appreciated.

    Bill Boucher
    http://www.biltronix.com

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Received on Thu Nov 3 09:47:51 2011