Re: 6809 pod problems

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My bad... looks like A5 is a resistor network and should be on during self
test.
-Adam

>From: "Adam Courchesne" <ajcrm125@hotmail.com>
>To: Eggwheatis@aol.com
>CC: techToolsList@flippers.com
>Subject: Re: 6809 pod problems
>Date: Tue, 15 Jul 2003 13:12:46 -0400
>
>
>It's low on the input and output of A5 because that interface IC only fires
>up when you are no doing self test. When you are doing self test, it gets
>its clock from the socket, which gets them from U22. U22 gets enables when
>you flip that switch to 6809E. And the input clock source to U22 comes
>from a clock divider (U21) that is clocked by by U23. So..... put the CPU
>connector in the socket and look at U22. If the output is low is it
>enabled? Is the input low? If it is is the clock divider running?
>If U22 is enables and the input is toggling but the output is low the I
>would suspect that the 6809E you are using in the micro socket might have
>gone bad is is pulling those lines low.
>
>Lemme know what you find...
>-Adam
>
>
>>From: Eggwheatis@aol.com
>>To: ajcrm125@hotmail.com
>>Subject: Re: 6809 pod problems
>>Date: Tue, 15 Jul 2003 12:32:03 EDT
>>
>>Hi Adam, Ok well the latest is I've been checking the clocks...The E clock
>>is
>>held low at the processor...The self test socket seems to output the Q and
>>E
>>clock ok, but as soon as you plug the the CPU connector in the self test
>>socket it holds the E clock low. It's low on the input and output of A5
>>the custom
>>interface(protection?) IC. What do you think?
>>
>>I really appreciate your time!
>>
>>Phil.
>
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Received on Tue Jul 15 12:08:31 2003