Re: FPGA

On Mon, 6 Oct 1997, Zonn wrote:

> My understading is that is takes four transistors per bit setup as a
> Set/Reset latch.

        SRAMs actually use 6 transistors per bit -- 4 for the 2 inverters,
plus 2 for the pass transistors.
  
> In DRAM they use 1 transistor and a capacitor. Unfortunately the capacitor
> will discharge quickly, so it must be *refreshed*.

        That's right -- it's 2 transistors -- one has the drain connected
to the source so that it acts like a capacitor.
 
> So I believe this makes DRAM nearly four times the storage density of SRAM
> for the same die size.

        That's hard to say -- it depends on the process, etc. Just
because DRAM uses a single transistor capacitor doesn't mean that the
capacitor transistor is the same size as one of the tranisitors in an SRAM
cell. DRAMs are VERY sensitive to processes, because things like leakage
currents, etc are VERY important in them....ANYways....

        As far as FPGAs go -- you can emulate an SRAM cell with a latch.
FPGAs don't care about transistors, though -- FPGA size is measured in
CLBs (Combinational Logic Blocks.) I remember Xilinx FPGAs of 2 or so
years ago had CLBs which could implement any function of 5 variables (the
CLB is SRAM based -- although you can think of it as a ROM) and each one
had a flip-flop. PROBABLY it will take 1 CLB per bit of memory, but since
those are SRAM based, I wonder if there is some hack to use the CLB as
however-many bits of SRAM. <shrug> That's as much as I know...

Joe
Received on Tue Oct 7 10:30:51 1997