Thanks for getting the stuff up so quickly, {Dave, Al}!
As far as complexity goes, this thing is SIMPLE. I will have a
Verilog model done TODAY.
Steve: Talk to me about your FPGA plans for this. I am almost
certain that an FPGA is not necessary. It will easily fit into an HD-PAL,
and maybe even 2 regular PAL/GALs.
How many people are interested in getting one of these? This
may be a likely candidate for a board run if there are enough people.
I am, for sure, going to make one for myself...
Joe
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Joseph J. Welser jwelser@ccwf.cc.utexas.edu
Design Engineer -- Crystal Semiconductor Corporation
Ph.D. Student in E.E. -- University of Texas at Austin
Work: jwelser_at_crystal.cirrus.com http://www.crystal.com
P.O. Box 17847; Austin, TX 78760
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On Wed, 15 Oct 1997, Al Kossow wrote:
>
> I've placed the zip file and the individual files in the schematics
> directory on www.spies.com
>
> http://www.spies.com/arcade/schematics/index.html
>
Received on Wed Oct 15 13:18:55 1997
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