On Mon, 18 Jan 1999, Anders Knudsen wrote:
> A reason the faster 2114 may be due to faster setup/hold times of the ram.
> That is, now you have a ram chip with a faster setup time, but more
> importantly in this case a faster hold time. So if the hold time is too
> fast, the data out may not be on the bus for a long enough time for other
> devices on the data bus. I havn't looked at the schematics, but it's
> conceivable that one could replace the other devices with faster ones,
> along with the faster rams, to compensate for the reduced hold times. It
> should be easy enought to trace the ram data path and find which device(s)
> (be they tri-state buffers, or whatever) are being affected by the reduced
> hold time of the faster rams.
>
> -----------
> a n d e r s
>
I think you're confusing hold time with ehhhh, something else....
Hold time is the time required after some edge for some signal
to be stable.
For example, there might be a spec on the Data input, with respect
to the Write Enable input, meaning that the Data must be held, even after
the write enable is de-asserted.
I think you're confusing hold time with transition time, but in
this context, I don't see how even that would be a problem. Shorter setup
and hold times will only help things. In practice, hold times are usually
very small, and often negative (for registers, for example.)
Maybe I totally missed what your were getting at though....
Joe
Received on Mon Jan 18 13:04:13 1999
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