Cinematronics CCPU on Xilinx FPGA

Hi,

Quick progress update, spacewars roms now modeled as block ram and
Modelsim is chucking out XY vectors :)
About 80 to 90 vectors per frame, most of them are really short, only
2us to 5us, I think they might be stars.

VHDL model is structural and a lot of it mimics the TTL on the CCPU, it
was the easiest approach given that I started with the schematic. It was
done this way so I could figure out how things worked. Don't think the
behavioral guys will like it :(

Next task is to clock it properly then start replacing the TTL. ALU,
comparator and shifter should be easy and all of the data path logic is
just 2:1 muxes.

Must get some ZZZs been up all night.

Chris
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Received on Tue Apr 7 03:32:13 2009