Freakin' sweet :-)! Your best QoR for area is going to be the gate level approach you are taking. The
tradeoff is "time to implement" in most cases.
Also, keep in mind that a behavioral design means exactly what it says...it doesn't mean it is synthesizable.
Moreover, if anyone tells you one way is better than another they are nuts. The example I sent you is more
abstract (i.e. RTL)...what's cool is that XST seems to do a decent job converting what I am "implying" when
I view the design using post-synthesis viewers. Still, area-wise, it will be no match to your results. For
designs like the CCPU, gate level is the way to go....I prefer the RTL approach since that's simply the way
I do things :-)!
Just a suggestion....goto www.fpgaarcade.com ... there is an Asteroids-on-a-chip package. In there,
MikeJ has a vector-to-VGA converter. You will need to add a ZBT SRAM model to your design.
You might be able to pump out some graphics....just be aware that what you see in simulation may not
match expected results graphics wise :-)!
What version of Modelsim are you using BTW?
Ed
PS OK...bedtime for real...tomorrow is going to be a long day.
________________________________
From: Chris Leyson <cleyson@aol.com>
To: vectorlist@vectorlist.org
Sent: Tuesday, April 7, 2009 3:31:48 AM
Subject: VECTOR: Cinematronics CCPU on Xilinx FPGA
Hi,
Quick progress update, spacewars roms now modeled as block ram and Modelsim is chucking out XY vectors :)
About 80 to 90 vectors per frame, most of them are really short, only 2us to 5us, I think they might be stars.
VHDL model is structural and a lot of it mimics the TTL on the CCPU, it was the easiest approach given that I started with the schematic. It was done this way so I could figure out how things worked. Don't think the behavioral guys will like it :(
Next task is to clock it properly then start replacing the TTL. ALU, comparator and shifter should be easy and all of the data path logic is just 2:1 muxes.
Must get some ZZZs been up all night.
Chris
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Received on Tue Apr 7 03:55:21 2009
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